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Edited by gf1 at 2019-3-17 05:49
Finally I had time to test the proposed modification. I've changed R61 to 1.5K as indicated, installed the last FW (20190312001) and run the calibration. I noticed some improvement but I still get glitchs in the waveforms
I had not yet change R61, because I didn't have a suitable 1k5 resistor at hand, so I only installed the firmware. Since the resistor change did not help for your device, I'll reneounce it.
Unfortunately I accidentally hit the Calibrate (F3) button (while I actually wanted to adjust the offset with F2 instead), and the AWG did re-calibrate (without asking for a confirmation), so my calibration is now ~2...3% off
@Amy:
In fact I still do not understand, why the proposed solution (increase the full-scale DAC current, thereby likely even exceeding the DAC's maximum value) were supposed to eliminate the glitches. My understanding is that it would only shift the glitches to a different vertical positions in the generated waveform.
You did not tell whether your engineer has already identified the root cause, or not.
My observation is that all occuring glitches are eventually located at particular absolute output voltage levels, which are integral mutiples of ~87mV on my device, and IMO these levels correspond to digital counts which are integral multiples of 64.
It is well known, and we have to live with the fact, that some DAC architectures do suffer from glitches, and assuming a segmented architecture with 32 segments (which is IMO likely for this kind of DAC models), the major-carry glitches are indeed supposed to happen at integral multiples of 1/64 of full scale (which is 4096/64=64 for a 12-bit DAC). This would fit with the observed picture. The size of the observed glitches does however not fit. The typical specified glitch energy for DA convertes like DAC902 or similar is as low as 3...5 pVs. But what I see at the AWG output is rather a glitch area of about 50mv * 20ns = 1000 pVs. Directly at the DAC outputs (before the amp) this still corresponds to ~170 pVs, so the spikes we see are IMO magnitutes larger than explainable by typical DAC glitches. So either your secret Chinese DAC model is of very low quality (compared to e.g. DAC902), or maybe you are overclocking them too much, or the root cause is not the DAC chip, but is still a different one.
Another potential reason coming into my mind are timing errors on the DAC's data inputs, with regard to the clock, and/or signal integrity errors (rise time, ringing,...) of these signals. The required setup und hold times of e.g. DAC902 are specified with 1ns and 1.5ns, so given 250MSPS (4ns period), there is only a time window of 1.5ns left where the data are allowed to change. If your secret Chinese DAC model has even larger setup/hold times, then it becomes even more challenging for the FPGA to output signals with the correct timing. I also don't see any damping resistors in the data lines from FPGA to DAC. I'm not sure if they are needed here, but on the other hand I see that you did install series resistors in the data lines from AD9288 to the FGPA (although they run at a slower clock). I can't verify/measure the timing, since this would require a MSO/LA with several GSPS, which I do not own, but likely your engineer can.
Yet another reason might be logical errors in the digital counts sent to the DAC. IMO this would be even the best case, since it could be fixed with a firmware or FPGA upgrade.
gf1
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