Over a few years using ISE 14.7, I became accustomed to the ways in which ChipScope didn't really work for all variations in work flow. I developed a specific regimen that I followed to make sure I got what I needed and got there on the first build, builds being so slow. For example, if I rebuilt my bitstream, I always had to create a new project and load the cdc file, recombine my busses and so forth -- every build. Doing anything shy of that and ChipScope would get confused about which signals were which.
So now I'm using Vivado for the first time, version 2017.1. I'm using Logic Analyzer for the first time. If I delete all the old logic-analyzer-related lines from my constraints file and then start from scratch, things work. But if I change my source code and rebuild, on the second time around I get miscellaneous warnings about things missing and eventually at the bitstream and logic analyzing, things misbehave. Darn. I thought the old ChipScope problems would be history. They're just a new set of problems and I don't yet have a regimen figured out to always work.